Power dissipation (P) of a device is dependent on capacitance (C), clock frequency (f) and supply voltage (V), with P=CfV2. The upper limit of the clock frequency is determined by supply voltage, thus a reduction in the supply voltage results in corresponding reduction in power dissipation. However, the reduction in the supply voltage of a device results in an increase in delay through the device which results in slowing down the execution time of an application.
When memory or an Input/Output (I/O) interface in a system is busy during run-time, for example, due to last-level cache misses to memory, computation performed by the processor is not on the critical path. For traditional server application workloads, cache-misses may account for 20% of processor cycles. Thus, when high computation speed of the processor is not required, the clock frequency/supply voltage of the processor may be reduced in order to reduce the energy consumption of the system. Typically, in order to reduce power dissipation, a processor may support multiple power states and provide a software interface for handling a request to change to a lower or higher power state.
Dynamic Voltage and Frequency Scaling (DVFS) is one technique that is typically used to provide power optimization during run-time. DVFS may be performed in hardware, in an operating system (OS), or in a user-level application. A hardware-level DVFS monitors processor load and scales the processor's supply voltage without involvement of software or OS. An OS-level DVFS uses heuristic scheduling based on a fixed time interval or scheduled tasks to perform DVFS. User-level DVFS enables a user application to profile processor utilization during execution and scale the processor's supply voltage or clock frequency up or down. Typically, a just-in-time (JIT) compiler is used to recompile the user application so that it can perform DVFS.
However, in a multi-threading environment, it is possible that one user application may scale down the processor's supply voltage and clock frequency, but another computation-intensive program may need a higher clock frequency before the supply voltage is scaled up. Thus, this results in extended execution time of the computation-intensive application.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.